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The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall drive a data word onto D[15:0].
b) The device shall generate a DSTROBE edge to latch the new word no sooner than t DVS after changing the
state of D[15:0]. The device shall generate a DSTROBE edge no more frequently than t CYC for the selected
Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more frequently
than 2tcyc for the selected Ultra DMA mode.
c)
The device shall not change the state of D[15:0] until at least tDVH after generating a DSTROBE edge to
latch the data.
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.
Figure 11: Sustained Ultra DMA Data-In Burst Timing
Notes: D[15:0] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to
be considered stable at the host until some time after they are driven by the device.
6.5.4.4.3 Host Pausing an Ultra DMA Data-In Burst
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in Figure 12:
Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Table 26: Ultra DMA Data Burst
Timing Requirements and are described in Table 27: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by negating – HDMARDY.
c) The device shall stop generating DSTROBE edges within t RFS of the host negating – HDMARDY.
d) If the host negates – HDMARDY within t SR after the device has generated a DSTROBE edge, then the host
shall be prepared to receive zero or one additional data words. If the host negates – HDMARDY greater
than t SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and t RFS
timing for the device.
e) The host shall resume an Ultra DMA burst by asserting – HDMARDY.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 32 of 102
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